In the field of micro-electronics, an electrostatic discharge generally results in a current spike that can be more or less intense flowing between two terminals of one or more components, associated with an increase in the voltage across the terminals of the component, and which could damage this or these components.
A device for protection against electrostatic discharges aims to absorb this current spike as much as possible in order to avoid the flow of this current within the component, while at the same time reducing the potential drop across its terminals in order to be compatible with the component to be protected.
There exist several solutions for the design of a device for protection against electrostatic discharges. A hybrid MOS transistor may, for example, be used such as that described in U.S. Pat. No. 9,019,666 (PCT/EP2011/050740), incorporated by reference, associated with a trigger circuit.
For example, this trigger circuit may be a resistive-capacitive circuit coupled to the control electrode of the MOS transistor.
In bulk substrate transistor technologies, the resistive-capacitive circuit may comprise the drain-gate and drain-substrate capacitances of the MOS transistor, and a resistor external to the MOS transistor coupled between ground and a terminal common to the substrate and to the gate of the MOS transistor. The use of the intrinsic capacitances of the transistor allows advantageously a gain of space.
However, in transistors fabricated on substrates of the SOI (Silicon-On-Insulator) type, these capacitances are greatly reduced and hence insufficient to be used as a capacitor for the resistive-capacitive trigger circuit.
On the one hand, the drain-substrate capacitance is greatly reduced owing to the smaller drain-substrate contact surface area, and on the other hand, the drain-gate capacitance is also reduced owing to the drain contact being made on an epitaxial region, further from the gate region.
Thus, when an electrostatic discharge occurs on an MOS transistor fabricated on a substrate of the silicon-on-insulator type, the voltage across the terminals of the transistor increases significantly, and the transistor only becomes conducting by means of the drain-source capacitance when the voltage across its terminals reaches a very high value, for example 7 volts.
When the voltage of 7 volts is reached, the transistor becomes conducting, which simultaneously leads to a voltage drop across the terminals of the transistor and an increase in the current flowing through it. This phenomenon is known by those skilled in the art under the term ‘snapback’.
It is therefore advantageous to limit this effect in order for the MOS transistor to trigger for lower voltages, and hence to be compatible with the load to be protected.